Scaling Compute

We’re funding two projects to develop software simulators to help the research community map the expected performance/power/cost for any future combination of algorithm, hardware, componentry, and system scale. The goal is to quantify the bottlenecks from different components in the stack, and enable agile adaptation to a fast-paced algorithms research community.

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Breaking Down the Compute Graph Step by Step: A Scalable and Modular Simulation

Aaron Zhao, Imperial College London; Luo Mai, University of Edinburgh; Robert Mullins, University of Cambridge

Team: George Constantinides, Wayne Luk, Imperial College London; Michael O’Boyle, University of Edinburgh; Timothy Jones + Rika Antonova, University of Cambridge

There is prevalent demand for performance estimation of the systems used in training frontier AI models. This project, co-led by teams from the University of Edinburgh, Imperial College London, and the University of Cambridge, focuses on the development of a scalable and modular performance simulation framework for future systems.

Heterogeneous Scale-out Platform Simulator

James Myers, Imec

Team: Nathan Laubeuf, Debjyoti Bhattacharjee, Abubakr Nada, Arjun Singh, Jonas Svedas and Diksha Moolchandani

This project imagines a future where compute infrastructure systems are designed with a heterogeneous mix of logic, memory and interconnect technology options, to mitigate the different scaling challenges. James and the team at Imec are building a software framework to estimate system efficiency and cost in these systems.

We know the movement of data has become as critical as raw computational power, so we’re funding two projects to interrogate system-level and advanced network design opportunities.

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Scalable AI Systems

Noa Zilberman, University of Oxford

Team: Amro Awad, Martin Booth, Nick McKeown, Dominic O’Brien, Patrick Salter

Noa and the team are aiming to introduce a new interconnect for scalable AI systems that solves the communication bottleneck. By rethinking communication at multiple levels and bringing together different disciplines, the project aims to revolutionise the design of AI systems.

Connectivity Technology for Sustainable AI Scaling

Tony Chan Carusone, Alphawave Semi

Team: Behzad Dehlaghi, Alphawave Semi

This project will develop and demonstrate the next generation of connectivity technologies for sustainable AI scaling. The Alphawave Semi team are reaching for hardware solutions that will enable 10,000s of AI accelerator chips to be interconnected across distances up to 150m with low cost and power consumption without limiting performance.

While the computing industry continues to progress an established path for improved performance, a variety of alternative ideas have emerged which harness noise, statistics, or unique physics in existing mass-manufacturable circuits to perform specific computing primitives. We’re funding seven teams to develop new technologies with the potential to open up new vectors of progress for the field of computing, with a targeted relevance for modern AI algorithms.

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CMOS Digital Thermodynamic Hardware Accelerator for Linear Algebra

Phillip Stanley-Marbell, Signaloid

Team: Bilgesu Bilgin, Apostolos Vailakis

Building on insights from analogue thermodynamic computing and randomised linear algebra, Phillip and the Signaloid team are looking to develop digital hardware to accelerate approximate matrix inversion.

Low-Precision Training using Backpropagation and Backpropagation-free Algorithms

Peter McMahon, Cornell University

This project aims to develop training methods that can leverage low-precision hardware, and to develop neural-network architectures that are better-suited to being trained with low-precision hardware. If successful, Peter’s team at Cornell will explore how well hardware designed for accelerating neural-network inference can be applied to training.

Thermodynamic Matrix Inversion

Patrick Coles, Normal Computing UK

Team: Gavin Crooks, Maxwell Aifer, Kaelan Donatella, Denis Melanson, Zachary Belateche, Samuel Duffield, Vincent Cheung

Patrick + the team at Normal Computing will build physics-based computing chips to invert matrices and explore applications in training large-scale AI models, targeting ~1000x energy savings over GPUs.

Better Analogue in Memory Matrix-vector Multiplication

Walter Goodwin, Fractile

Walter and the team at Fractile aim to demonstrate that analogue in-memory compute can drive the world’s highest density and most efficient matrix-vector multiply operations. Their goal is to leverage the developed approaches in Fractile’s inference acceleration hardware to run frontier models orders of magnitude faster than current state of the art. Whether sufficient precision can be achieved for application, in theory, to large scale training systems remains an open question.

Neuromorphic Matrix Multiplication

Bipin Rajendran, King’s College London

Team: Osvaldo Simeone, Kai Xu

Combining the multiplicative advantages that arise from (i) event-driven, backprop-free learning algorithms, (ii) stochastic computing, and (iii) in-memory computing based on Si CMOS technology, Bipin and the team will design and demonstrate a neuromorphic framework to reduce the cost of developing AI models.

Energy-Efficient SRAM-Based Analogue Accelerator for Second-Order Optimisation

Jack Kendall, Rain AI UK

Jack’s team from Rain AI are looking to develop a novel accelerator architecture for performing fast vector-matrix inverse multiplication using digitally-programmable transistor arrays with feedback control.

Shortening the Salesman’s Travel: Massive Parallelism for Combinational Optimisation Problems

Marian Verhelst, Wim Dehaene, KU Leuven

Team: Toon Bettens, Sofie De Weer

Marian and the team at KU Leuven are targeting a new class of mixed-signal processors that are specifically conceived to solve combinatorial optimisation problems.

Training Analogue Electrical Networks with Equilibrium Propagation

Benjamin Scellier, Rain AI UK

Ben’s team from Rain AI aims to demonstrate, through simulations, the feasibility of training analogue hardware with Equilibrium Propagation of the size of modern deep learning architectures.