Why this programme

The digital electronics industry that has transformed our lives in immeasurable ways is defined by the simple fact that, for 60+ years, we have benefited from exponentially more computing power, at a continually lower cost. 

This fact is no longer true. For the first time in history, increased performance requires increasing costs and this coincides with an explosion of demand for more compute power driven by AI. 

Our current mechanisms for training AI systems utilise a narrow set of algorithms and hardware building blocks, which require significant capital to develop and manufacture. The combination of this significance and scarcity has far-reaching economic, geopolitical, and societal implications.

What we’re shooting for

We see an opportunity to draw inspiration from natural processing systems, which innately process complex information more efficiently (on several orders or magnitude) than today’s largest AI systems.

Our goal: to increase + open up new vectors of progress in the field of computing by bringing the cost of AI hardware down by >1000x.

We’re bringing expertise across three critical technology domains (AI systems design, mixed-signal CMOS circuits, and advanced networking) and a strong institutional mix (spanning academia, non-profit R&D organisations, startups and multinational companies), as we look to pull novel ideas to prototypes and into real-world applications. 

If successful, this programme will unlock a new technological lever for next-generation AI hardware, alleviate dependence on leading-edge chip manufacturing, and open up new avenues to scale AI hardware – an industry which is worth trillions of pounds. 

We’re also delighted that the programme’s ambition has drawn ambitious international organisations to either establish or expand their UK operations – a crucial step in building the UK’s capabilities in this field.

1| Charting the Course

2| Advancing Networking and Interconnect

3 | New Computational Primitives

Breaking Down the Compute Graph Step by Step: A Scalable and Modular Simulation
Project leads: Aaron Zhao, Imperial College London; Luo Mai, University of Edinburgh; Robert Mullins, University of Cambridge
Team: George Constantinides, Wayne Luk, Imperial College London; Michael O’Boyle, University of Edinburgh; Timothy Jones and Rika Antonova, University of Cambridge

There is prevalent demand for performance estimation of the systems used in training frontier AI models. This project, co-led by teams from the University of Edinburgh, Imperial College London, and the University of Cambridge, focuses on the development of a scalable and modular performance simulation framework for future systems.

“The most exciting aspect is the breadth of cross-domain expertise, ensuring a thorough examination of all aspects of current machine learning systems and opening avenues for potential groundbreaking discoveries in this field of research.”

Connectivity Technology for Sustainable AI Scaling
Project lead: Tony Chan Carusone, Alphawave Semi
Team: Behzad Dehlaghi, Project Technical Lead

This project will develop and demonstrate the next generation of connectivity technologies for sustainable AI scaling. The Alphawave Semi team are reaching for hardware solutions that will enable 10,000s of AI accelerator chips to be interconnected across distances up to 150m with low cost and power consumption without limiting performance.

“We’re excited about Scaling Compute’s potential to impact daily life by catalysing AI innovations that will advance healthcare, education, the environment, and beyond.”

CMOS Digital Thermodynamic Hardware Accelerator for Linear Algebra
Project lead: Phillip Stanley-Marbell, Signaloid
Team: Bilgesu Bilgin, Apostolos Vailakis

Building on insights from analogue thermodynamic computing and randomised linear algebra, Phillip and the Signaloid team are looking to develop digital hardware to accelerate approximate matrix inversion.

“There is currently a missed opportunity to exploit insights from analogue computing systems to enable more efficient analogue and digital hardware for speeding up linear algebraic kernels.”

Better Analogue in Memory Matrix-vector Multiplication
Project lead: Walter Goodwin, Fractile
Team: Fractile Team

Walter and the team at Fractile aim to demonstrate that analogue in-memory compute can drive the world’s highest density and most efficient matrix-vector multiply operations. Their goal is to leverage the developed approaches in Fractile’s inference acceleration hardware to run frontier models orders of magnitude faster than current state of the art. Whether sufficient precision can be achieved for application, in theory, to large scale training systems remains an open question.

“This is a nascent technology and we think we can reach even more energy efficiency. There’s a whole frontier to be explored.”

Energy-Efficient SRAM-Based Analogue Accelerator for Second-Order Optimisation
Project lead: Jack Kendall, Rain AI UK
Team: Maxence Ernoult, Greg Kollmer, Georgios Konstadinidis, and six UK team members to be hired

Jack’s team from Rain AI are looking to develop a novel accelerator architecture for performing fast vector-matrix inverse multiplication using digitally-programmable transistor arrays with feedback control.

“The Scaling Compute programme enables researchers across many disciplines, from machine learning to photonics, analogue computing, and materials science, to come together under one roof with the unified goal of creating new paradigms of energy-efficient AI systems.”

Suraj aims to redefine the way computers process information. He is directing funding into how we can build more efficient computers using principles ubiquitously found in nature.

Prior to ARIA, Suraj was co-founder and CTO of Sync Computing, a VC-backed startup optimising the use of modern cloud computing resources. The company was spun-out from his research at MIT Lincoln Laboratory. Prior to that, Suraj worked at Intel Corp, helping transition silicon photonics technology from an R&D effort into a now >$1BN business.